SI5351A clock jitter

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karl_nottkarl
 
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SI5351A clock jitter

Post by karl_nottkarl »

I just hooked up the SI5351A to a Rigol DS1102E and I'm able to observe the sample code frequencies, however, there's a good amount of clock jitter. If I set the frequency to a whole number using integer only mode, such as 50Mhz (25Mhz * 16 / 8), the frequency holds at exactly 50Mhz.

If I use the same integer only mode to generate a fractional frequency such as 46.875Mhz (25Mhz * 15 / 8), the scope flips between 46.73Mhz and 47.17Mhz, never quite hitting the mark. Is this a function of my base level scope, or is this type of fluctuation to be expected?

Thanks,
Karl

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adafruit_support_mike
 
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Re: SI5351A clock jitter

Post by adafruit_support_mike »

You'll see that on any digital scope. It's basically a rounding error.

DSOs are bascially integer devices. The screen is X units of time wide and Y units of voltage high, and all values fall exactly on one of the integer X-Y points. You can fudge that a little by drawing multiple samples on the screen and taking the average, but that just makes the X and Y unit steps smaller than the resolution of any single sample.

The two frequencies you quoted are 440kHz apart, which translates to a tolerance of about +/- 1us per cycle. What timebase were you using when you took the reading?

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karl_nottkarl
 
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Re: SI5351A clock jitter

Post by karl_nottkarl »

Time base was set to 10ns.

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adafruit_support_mike
 
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Re: SI5351A clock jitter

Post by adafruit_support_mike »

Hm.. looks like I bungled the error margin.

The period of a 46.73 MHz wave is about 21.4ns. The period of a 47.17 MHz wave is about 21.2ns. The difference between those is about 200 picoseconds, for a tolerance of +/-100ps.

The DS1102E has single-channel sampling rate of 1Gsps, or 1ns between samples. 100ps is 10% of that, which is a conservative estimate on jitter for the sampling clock.

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karl_nottkarl
 
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Re: SI5351A clock jitter

Post by karl_nottkarl »

Thanks for the clarification, much appreciated. On a side note, what type of scope was used in the guide for this part. It seemed to have captured the numbers perfectly in the screenshots.

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Re: SI5351A clock jitter

Post by adafruit_support_mike »

I don't know that one personally, but the images show it's a Tek sampling at 5Gsps, and the frequency counter goes to 1GHz. I'd put it somewhere in the DPO4000/4100 series.

I'll ask around.

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Re: SI5351A clock jitter

Post by adafruit2 »

hiya, finally an easy Q for me :) It's an Tek MDO3104 which is pretty nice except i cant figure out how to measure with cursors. to be completely honest, it was given as a gift from tek - i probably would not have shelled out for it! my previous scope, the TDS2014 is still much beloved!

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karl_nottkarl
 
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Re: SI5351A clock jitter

Post by karl_nottkarl »

That's quite a gift. :)

I wanted to give this thing a decent test, so had it replace an 8Mhz crystal for a microcontroller and also provide the 3.579545Mhz clock to a contact javacard, successfully passing data over a t=0 protocol.

The one thing I did see in the datasheet which I couldn't find any further detail on was configuring the Si5135A's nvram to store a default configuration. Is that something that can only be done at factory time?

Without that kind of defaulting, replacing the crystal on a microcontroller first seems to involve having something else (another microcontroller in this case) configure the Si5135A at power up. .

Thanks!
Karl

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adafruit_support_mike
 
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Re: SI5351A clock jitter

Post by adafruit_support_mike »

It looks like the default configuration is a factory-only thing. The datasheet links to a program that generates a configuration spec and sends it to Silicon Labs for production.

Our breakout is designed to be a microcontroller peripheral rather than a microcontroller driver, so it probably wouldn't be a good choice as a boot-time crystal replacement.

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karl_nottkarl
 
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Re: SI5351A clock jitter

Post by karl_nottkarl »

Thanks for looking into it. At the moment it's doing a good job of supporting one microcontroller running at 16Mhz and another at 8Mhz, with the breakout driven by a third.

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Re: SI5351A clock jitter

Post by adafruit_support_mike »

Hey, as long as it works, you win! ;-)

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jmg
 
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Re: SI5351A clock jitter

Post by jmg »

karl_34 wrote: The one thing I did see in the datasheet which I couldn't find any further detail on was configuring the Si5135A's nvram to store a default configuration. Is that something that can only be done at factory time?
Yes, it is only factory Set, but there are some pre-configured part codes out there
If you drop this part code that is mentioned as one option in the Breakout BOM,

Si5351A-B02075-GT

into the Silabs partcode Lookup under Clocks.

http://www.silabs.com/products/clocksos ... -B02075-GT

you can get this Config file below, and also addendum link has Si5351A-B02075-GT_datasheet_addendum.pdf
which is a shorter PDF version of the Config file below.

: 27MHz -> 24.576 or when corrected for the 25MHz Xtal,
24.576*25/27 = 22.7555555MHz

Even if you buy a pre-config device, there is a risk if you reconfig over i2c from the MCU, as reset and PLL lock will interrupt the clock out, and any program error will remove the CLKOUT, or move it 'out of spec'.

It would be nice if Silabs had made the option of locking one VCO/PLL/Divider for MCU use.

Code: Select all

# Do not modify the contents of this file.
# This file is for factory NVM programming.
#BEGIN_PROFILE
# Name: 1
#Profile = 1
#BEGIN_HEADER
# Date = Thursday, February 21, 2013 21:38
# File version = NVM 3
# Software Name = ClockBuilder Desktop Software
# Software version = 6.0.0
# Software date = December 13, 2012
# Chip = Si5351A
# Part Number = Si5351A-x-GT
#END_HEADER
# I2C address = 0x6F
#XTAL (MHz) = 27.000000000
#Mode = Automatic
#PLL A
# Input Frequency (MHz) = 27.000000000
# F divider = 1
# PFD (MHz) = 27.000000000
# VCO Frequency (MHz) =  737.280000000
# Feedback Divider = 27  23/75
# Internal Load Cap (pf) = 10
# SSC disabled
#PLL B
# Input Frequency (MHz) = 0.0
# VCO Frequency (MHz) =  0.0
# Pull Range (ppm) = 0.0
#Output Clocks
#Channel 0
# Output Frequency (MHz) = 24.576000000
# Multisynth Divider = 30
# R Divider = 1
# PLL source = PLLA
# Initial phase offset (ns) = 0.000
# Error (ppm) = 0.0000
# Powered = On
# Inverted = No
# Drive Strength (mA) = 8
# Disable State = Low
#Channel 1
# Powered = Off
#Channel 2
# Powered = Off
#Channel 3
# Powered = Off
#Channel 4
# Powered = Off
#Channel 5
# Powered = Off
#Channel 6
# Powered = Off
#Channel 7
# Powered = Off
#
#REGISTER_MAP
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#END_REGISTER_MAP
#END_PROFILE
# CHECKSUM = EB8087DB9297BE82D2CD262B19E83CE135CB6D79

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