Shutting down GPIOs during ISP programming

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kumashiro
 
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Shutting down GPIOs during ISP programming

Post by kumashiro »

Hello

First of all I would like to apologize for my poor English. If anything is unclear, please let me know and I'll try to explain what I mean.

During (re)programming of ATmega chips, GPIOs are flapping randomly (?), which is expected. However, when I have other integrated circuits connected to the microcontroller, they go absolutely bonkers during that time. I already destroyed one (quite expensive) device that way. I'm looking for a solution to this problem. How can I "disable" GPIOs during (re)programming? I could use MOSFETs to block other chips (switch them to ignore inputs), but not all of the ICs have such feature, there are differences in levels that activate it (some can be blocked by a HIGH level, others by LOW) and I would really like to avoid putting additional logic or MOSFET inverters to do just that. I could also reprogram the microcontroller in a ZIF socket, but that won't work with SMT elements. How do you handle this problem?

Thank you.

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adafruit_support_mike
 
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Re: Shutting down GPIOs during ISP programming

Post by adafruit_support_mike »

The signals that go to the other chips probably won't require much current, so putting a 1k resistor between the chips probably wouldn't hurt.

Once you have a resistor, put a test point on the side farthest from the microcontroller, and closest to the chip you want to protect.

Then make a jig with pins that touch all the test points and supply whatever voltage you want:
probe.jpg
probe.jpg (14.18 KiB) Viewed 918 times
That way the microcontroller pin can do whatever it wants while the probe holds the other chip's pin at a safe value.

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brucef
 
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Re: Shutting down GPIOs during ISP programming

Post by brucef »

I'm guessing here that "flapping randomly" means floating? While the AVR is being programmed, most of the I/O pins are in high impedance mode so it's almost as if they aren't connected to the circuit at all. The exception would be the SPI or UART pins, depending what interface you're programming over.

If that's what you're dealing with, I think you might more need to use something like 10k pull up or pull down resistors on any critical floating I/O pins.

Or I could be entirely misunderstanding your problem...

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Cjuried
 
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Re: Shutting down GPIOs during ISP programming

Post by Cjuried »

A little trick I have been using exploits the use of the reset pin being held at 5 volts under normal operation and being pulled down to GND 0v when the chip is flashed. I use a FET, 2N7000 or similar, as a switch in between my external component's ground rail controlled by the reset pin. Therefore when I flash a chip the reset pin sends 0v to the gate of the fet and the ground rail is therefore disconnected, which will open up those pins for programming. Once the chip is flashed the 5v control signal, from the reset pin, returns to the gate, of the fet, and the ground rail is reconnected allowing the chip to use the GPIO's as programmed.

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kumashiro
 
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Re: Shutting down GPIOs during ISP programming

Post by kumashiro »

It seems that AVR GPIOs are flapping between high and low levels during programming. That's a problem. They are definitely not floating. I could pull up or pull down "external" chips inhibiting inputs during programming, but with many ICs on a board this may be troublesome. Pogopins are too invasive and require access to the whole board during programming, which means I could not flash AVR on a circuit enclosed in a box.

I came up with two solutions: I can divide the power rail into two lines - AVR and "external" chips. This division can be bridged by S-D side of N-channel power FET. The gate can be pulled down to ground by my custom ISP connector or (since I'm using 5V everywhere) when power supply voltage is below 4.0V. That way, the "external" chips will be cut off from power when ISP is connected or when I'm programming the AVR with a 3.3V programmer (ATmega doesn't care; it can run on 3.3V or 5V).

Thanks guys :)

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brucef
 
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Re: Shutting down GPIOs during ISP programming

Post by brucef »

kumashiro wrote: It seems that AVR GPIOs are flapping between high and low levels during programming. That's a problem. They are definitely not floating.
That doesn't sound right to me.

According to the ATmega328P datasheet, section 1.1 (Pin descriptions): "The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running." There are similar statements in that section for ports C and D. That covers all I/O on the chip except for a couple of packages with extra ADC-only pins, which are by definition input-only. So when the chip is reset, all I/O is floating. Maybe you're using a different chip, but I expect they all behave the same in this regard.

From that state, it is my understanding that pins will only leave this tri-state configuration if you start programming the chip over the ISP interface or if reset is released and the on-chip program starts configuring them.

Looking at the AVR In-System Programming datasheet, only the SPI pins (MOSI/MISO/SCK) are active during the ISP process. Every other I/O pin should remain tri-stated, i.e. floating.

Is the issue here that you're using the SPI pins in your design without suitable isolation for programming? Otherwise, which pins are causing the problem? Exactly which chip are you using, anyway?

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