pll tuning uses wrong crystal fq or c code??

[inh]

Hi there - I've noticed that I am jamming some cell channels effectively, but not others, so I checked the voltage ranges going into the VCOs of my 2 working units so far. The voltages should be 4-6v on VCO2, and 2-6v on VCO1, for fq jamming of 860-960Mhz and 1640-2220Mhz respectively - read from the VCO datasheets.

Actually on both units I am getting different ranges - 3-4.5v on VCO2 and 4-7v on VCO1. Because this is happening on both units, I am suspicious of the pll tuning...

I have an Aaronia spectrum analyser arriving next week, but I thought I'd check the PLL code anyway. I am not a good c programmer (more VB), but I notice that main.c calls pll_init, and when you look inside pll.c, you can see that pll_init has a reference to a 1Mhz clock. Could it be that we should use a 1Mhz clock???

Anyone who understands this code better than me would be very useful to hear from...

[Lanmasterd]

ive never really looked at any of the files apart from trhe main.c file..
but yeah u are rite i have a 1mhz ref too.. me thinking maybe this might be a typo or mistake.. im wounder would it cause damage to change this to a 10mhz.. ???
im new myself to the pll code but im gonna spend the next 2 days looking into it..
ill be doing up my work lab in my home pffice too so ill have results of my test too i hope..
oh and inch nice catch on the gain block u mentioned.. i replyed to it on the wavecaster forum
Lanmasterd

[inh]

Hi Lanmasterd - please note that I don't fully understand the c code for the pll_init routine (also 1Mhz is mentioned in the pll_set_rcounter routine). In fact I can only see it mentioned in the commented out notes, so I don't know whether it is a choice which is even relevant in the actual compiled code. But it may be...

In my next digikey order I'm going to get some 1Mhz crystals (and some of those SXB-4089Zs) and see if anything changes if I substitute them - maybe it'll get the voltages going into the VCOs in the right range, maybe not...

In the mean time - we need to understand whether the c code controlling the pll is explicitly telling the pll to refer to a 1Mz signal, when we infact are giving it a 10Mhz signal...

[inh]

could it be that r8 and r9 are needed to pull VCO1 and VCO2 DCADJ to gnd? ie not let voltages on c22/c23 stay high - the VCOs wont drain much away... Looks like the principle of a SMPS without r8 and r9...

I haven't installed them...
any suggestions for values?