PLL Help

[grapeape]

Hi All,

I've been building and testing for some time and am having difficulty with the PLL stage. When I program test_pll1() I am seeing a 5Hz wave on pin 10, where the documentation indicates I should be seeing 1Hz. The crystal is being driven correctly and the regulator is working. Any thoughts?

Attempting to tune a program generates the "RF VCO range is too low!" message, which would suggest that my PLL isn't functioning.

Cheers,
John

[grapeape]

Can anyone think of further tests to isolate the problem? I'm really quite lost at this point.

[Buggy222]

On the laydada webpage follow the Wiki link and look at the "Make" link, and then the PLL. You will see a notation that the frequency will be 5 not 1.

http://ladyada.net/wiki/wavebubble/pll

PLL Notes
when running the test_pll1 code. the rc1a firmware will set Ftest(pin 10) to 5hz (not 1hz as per the pll docs).

[grapeape]

Thanks Buggy. Not sure how I missed that note.

Is there a good reference around for debugging the PLL stage? I've been stuck here for quite a while. While the PLL section of the Make pages describes the tests to verify functionality along the way, it doesn't offer much help when one of the tests fails.

[Bandit]

Did you get the other PLL test programs working? Im having problems with those, when I probe the middle of the two resistors for each stage as directed. Im not getting the switch over between around 0V and 2.1V

[c.b.]

Hi Bandit,

I had problems, too, at that stage. I had forgotten to solder the resistor that connects the VCO's outputs to the PLL chip. Some HF went to the PLL chip through the air or I don't know how, anyway sometimes the PLL output flipped and sometimes not.

[Bandit]

I thought that might be the case so I placed some copper tape over the gap in the track. I would have thought some of the signal would be coupled throught both the air and the FR4 substrate, moreso through the substrate. I'll try putting the resistors on. Thanks.