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Understanding logic gate NOT
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Understanding logic gate NOT

by Tuom Larsen on Mon Aug 23, 2010 6:16 pm

Hello,
I'm totally new into EE and I'm tryinh to understand how logic gates really work, with the help of trying to visualize transistors as ordinary switches. AND becomes a wire connected to +5V and two switches in series, OR two switches in parallel, like:

Code: Select all | TOGGLE FULL SIZE
              /      /
AND:  +5V ---o o----o o----

                   /
             +----o o----+
OR: +5V   ---+     /     +-----
             +----o o----+



But I'm having hard time to come up with an analogy to NOT gate. Please, could someone help me here? Perhaps this is not the best way how to picture the things in the first place...
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Re: Understanding logic gate NOT

by westfw on Mon Aug 23, 2010 9:30 pm

By analogy with your current diagrams, simply think of a "not" gate as a "normally closed" switch that connects to +5V when "off" and disconnects when "on."

It all gets more complicated when you consider that in the "0" state, you normally want to be "connected" to 0V, which is not the same things as just "disconnected."

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Re: Understanding logic gate NOT

by Tuom Larsen on Wed Aug 25, 2010 9:07 am

Thanks for the reply!

However, I was kind of thinking it could be somehow done with "regular" switches, i.e. on means on, and vice versa.

Would this work? Why isn't half of the +5V leaking even if the switch is on?

Code: Select all | TOGGLE FULL SIZE


NOT:  +5V  ----+---- Output
               |
               o
                \
               o
               |
             -----  (or just "-" ("minus")?)
              ---
               -

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Re: Understanding logic gate NOT

by pstemari on Wed Aug 25, 2010 11:52 am

To do this with switches and true=+5v/false=high impedance, you'd either need to use an NC relay or just reverse the label on the switch.
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Re: Understanding logic gate NOT

by westfw on Wed Aug 25, 2010 12:52 pm

Your second circuit would short out the power supply when the switch was closed, possibly leading to "excitement." However, if you were to use a "pull up" resistor to +5V to limit the current when the switch is close, then it would work (and incidentally be very similar to Arduino "button" examples that use a pullup resistor - the pin will indeed read "0" when the button is pressed.)
But a resistor is an "advanced" electronic component compared to switches; if you have only switches, you need the NC switch or reversed labels.

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Re: Understanding logic gate NOT

by Tuom Larsen on Wed Aug 25, 2010 3:40 pm

Ok. But if I add that "pull up" resistor in the schematic above:

Code: Select all | TOGGLE FULL SIZE
NOT:  +5V  ----+---- Output
               |
               o
                \
               o
               |
              +++
              | |
              | |
              +++
               |
             -----  (or just "-" ("minus")?)
              ---
               -



the output wouldn't be +5V while switch being closed ("on"), right? And also it would consume some additional power, due to the resistor, right? Is there a way to make it again either +5V or ... 0V (what exactly? ground?)?

To put in in different way, I understand the option of changing the labels, it just seems to me that while AND and OR gates could be conceptually modeled via switches in pretty straight forward way, the NOT gate with changed label is something a bit different because it does not create +5V out of nothing ("on").
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Re: Understanding logic gate NOT

by pstemari on Wed Aug 25, 2010 10:01 pm

There just not a good way to show it with toggle switches. Try this with pushbuttons:

Code: Select all | TOGGLE FULL SIZE
NOT:

                      |
          +5V  ----o  |  o---- Output
                   ---+---


NOT NOT:

                      |
                      |
                   ---+---

          +5V  ----o     o---- Output
--Paul

A wholly owned subsidiary of:
Persephone: DL R+W+B C 7 X L W C++ I++ T+ A E H++ S+ V-- F+ Q P B PA+ PL
Aldebaran: DM Rt H 5 Y L- W+ C+ I++ T++ A+++ E H++ S+ V+ F++ Q+ P B++ PA- PL--
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Re: Understanding logic gate NOT

by westfw on Wed Aug 25, 2010 11:11 pm

your pullup picture is wrong. It should be:
Code: Select all | TOGGLE FULL SIZE
        +-----+
+5V ---o+  R  +o---+--- Out: Not "x"
        +-----+    |
                   o
                    \ "x"
                   o
                   |
                  GND

When the switch is open, the resistor provides 5V to the output. When the switch is closed, it forces the output to GND, since the switch resistance is zero. (There are certain "not practical" aspects of this, of course. Which is why it is difficult to design complicated circuits using switch-based logic (ie Relays.) This is essentially the function of transistors, especially in some of the older logic families like RTL and DTL. They amplify the non-ideal signals back to "close to ideal" (at some expense in other areas.)

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Re: Understanding logic gate NOT

by stinkbutt on Tue Oct 26, 2010 12:04 pm

This is a transistor version of a NOT gate:

Image

Does that clear things up? When the input's low the transistor's off, so it gets pulled high. Input goes high, transistor turns on & pulls it low. This is pretty much the same thing the other gents are posting to explain it, only I don't imagine ASCII art is the clearest way to explain things.
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