I needed to adjust the clock source to RTC and stumbled across a confusing thing in samd21_clocks.c file.
There is this function:
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void clock_init(void)
{
init_clock_source_osc8m();
if (board_has_crystal())
init_clock_source_xosc32k();
else
init_clock_source_osc32k();
enable_clock_generator(0, GCLK_GENCTRL_SRC_DFLL48M_Val, 1);
enable_clock_generator(1, GCLK_GENCTRL_SRC_DFLL48M_Val, 150);
init_clock_source_dfll48m();
if (board_has_crystal())
enable_clock_generator(2, GCLK_GENCTRL_SRC_XOSC32K_Val, 32);
else
enable_clock_generator(2, GCLK_GENCTRL_SRC_OSC32K_Val, 32);
}
So, I looked what that function does:
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void enable_clock_generator(uint8_t gclk, uint32_t source, uint16_t divisor) {
uint32_t divsel = 0;
if (gclk == 2 && divisor > 31) {
divsel = GCLK_GENCTRL_DIVSEL;
for (int i = 15; i > 4; i++) {
if (divisor & (1 << i)) {
divisor = i - 1;
break;
}
}
}
GCLK->GENDIV.reg = GCLK_GENDIV_ID(gclk) | GCLK_GENDIV_DIV(divisor);
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk) | GCLK_GENCTRL_SRC(source) | divsel | GCLK_GENCTRL_OE | GCLK_GENCTRL_GENEN;
while (GCLK->STATUS.bit.SYNCBUSY != 0) {}
}
So, at least two of four calls to that function make no effect:
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enable_clock_generator(0, GCLK_GENCTRL_SRC_DFLL48M_Val, 1);
enable_clock_generator(1, GCLK_GENCTRL_SRC_DFLL48M_Val, 150);
And yes, I checked - that is not another leftover (of which there is tons in this code). clock_init() will be called from supervisor/port.c:port_init()
So, if someone has problems with clock signal being too slow/fast than expected (announced?), RTC drift or timer interval other than set up - check the generator you are driving your peripherals from. Only generator 2 will work adequately.
regards