I'm not sure as this is my first foray into the dark world of clocks but I think it's running from a 48MHz source (
peripheral_clk_config.h#L330) divided by 24 (
hpl_gclk_config.h#L466) to give 2MHz for DAC. With 12 clock cycles per conversion (ignoring for the moment the extra settle 12 time) then that could be what's capping output rate to 166.667kHz?
Is there a 12MHz clock available to get this up to max 1Msps output rate? It looks like
CONF_DAC0_CCTRL and
CONF_DAC1_CCTRL need to go to 2 for this setting.
Could
CONF_DAC0_CCTRL and
CONF_DAC1_CCTRL with value of
1 be the cause of the voltage limitation discussed in
PyGamer DACs limited to 2.5V - 2.6V ?? If it's refusing to supply more than 2.5V/200ohm = 12.5mA at value
1 that could explain this max value?