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Debug UART port on Metor ESP32-S2 board
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Debug UART port on Metor ESP32-S2 board

by jfabernathy on Tue Jan 12, 2021 9:09 am

From what I've read, the Debug UART port on the Metro ESP32-S2 is for use with a Debug enabled Circuitpython build.

In preparation for needed to go that route I connected a USB-Serial UART cable to the Metro ESP32-S2 using stake pins I soldered on. I was surprised to see data already coming out. It was good to see but not very useful because it contained no CP error messages. I'm running CP 6.10 RC1.
This is what I see:
Code: Select all | TOGGLE FULL SIZE
ESP-ROM:esp32s2-rc4-20191025
Build:Oct 25 2019
rst:0x5 (DSLEEP),boot:0x8 (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:2
load:0x3ffe6100,len:0x8
load:0x3ffe6108,len:0x1af8
load:0x4004c000,len:0x213c
load:0x40050000,len:0x1c08
SHA-256 comparison failed:
Calculated: de141682c15256bb0f9b36c26014badeed37137f77ff10226efbc94a6e9f15dc
Expected: eaba5157ca2febb03a07fd9f256427539492daf9ecb772aef91e2ccbae79deb3
Attempting to boot anyway...
entry 0x4004c4c4
I (69) boot: ESP-IDF v4.3-dev-1197-g8bc19ba89 2nd stage bootloader
I (69) boot: compile time 22:08:57
I (69) boot: chip revision: 0
I (72) qio_mode: Enabling default flash chip QIO
I (77) boot.esp32s2: SPI Speed      : 40MHz
I (82) boot.esp32s2: SPI Mode       : QIO
I (87) boot.esp32s2: SPI Flash Size : 4MB
I (92) boot: Enabling RNG early entropy source...
I (97) boot: Partition Table:
I (101) boot: ## Label            Usage          Type ST Offset   Length
I (108) boot:  0 nvs              WiFi data        01 02 00009000 00005000
I (115) boot:  1 otadata          OTA data         01 00 0000e000 00002000
I (123) boot:  2 ota_0            OTA app          00 10 00010000 00160000
I (131) boot:  3 ota_1            OTA app          00 11 00170000 00160000
I (138) boot:  4 uf2              factory app      00 00 002d0000 00040000
I (146) boot:  5 ffat             Unknown data     01 81 00310000 000f0000
I (153) boot: End of partition table
I (158) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f000020 size=0x390ec (233708) map
I (218) esp_image: segment 1: paddr=0x00049114 vaddr=0x3ffcd9e0 size=0x031d0 ( 12752) load
I (222) esp_image: segment 2: paddr=0x0004c2ec vaddr=0x40028000 size=0x00404 (  1028) load
I (225) esp_image: segment 3: paddr=0x0004c6f8 vaddr=0x40028404 size=0x03920 ( 14624) load
I (238) esp_image: segment 4: paddr=0x00050020 vaddr=0x40080020 size=0xe1454 (922708) map
I (448) esp_image: segment 5: paddr=0x0013147c vaddr=0x4002bd24 size=0x11cbc ( 72892) load
I (469) esp_image: segment 6: paddr=0x00143140 vaddr=0x40070000 size=0x0001c (    28)
I (469) esp_image: segment 7: paddr=0x00143164 vaddr=0x50000000 size=0x01000 (  4096)
I (487) boot: Loaded app from partition at offset 0x10000
I (487) boot: Disabling RNG early entropy source...
I (500) cache: Instruction cache        : size 16KB, 4Ways, cache line size 32Byte
I (500) cache: Data cache               : size 16KB, 4Ways, cache line size 32Byte
I (506) spiram: Found 16MBit SPI RAM device
I (510) spiram: SPI RAM mode: sram 40m
I (515) spiram: PSRAM initialized, cache is in normal (1-core) mode.
I (522) cpu_start: Pro cpu up.
I (526) cpu_start: Application information:
I (530) cpu_start: Project name:     circuitpython
I (536) cpu_start: App version:      6.1.0-rc.0
I (541) cpu_start: Compile time:     Jan  6 2021 03:44:46
I (547) cpu_start: ELF file SHA256:  7dcf3254c7f96ef5...
I (553) cpu_start: ESP-IDF:          v4.2-48-gebe778425
I (559) cpu_start: Single core mode
I (974) spiram: SPI SRAM memory test OK
I (974) heap_init: Initializing. RAM available for dynamic allocation:
I (974) heap_init: At 3FF9E01C len 00001FE4 (7 KiB): RTCRAM
I (980) heap_init: At 3FFD9EC0 len 00022140 (136 KiB): D/IRAM
I (987) heap_init: At 3FFFC000 len 00003A10 (14 KiB): DRAM
I (993) cpu_start: Pro cpu start user code
I (1734) phy: phy_version: 603, 72dfd77, Jul  7 2020, 19:57:05, 0, 2
W (1734) wifi: start
W (4624) wifi: connected
W (6114) wifi: got ip
W (6414) wifi: disconnected
W (6414) wifi: reason 8 0x08
W (6414) wifi: stop
I tried to create a uart object using:
Code: Select all | TOGGLE FULL SIZE
uart = busio.UART(board.TX, board.RX, baudrate=115200)
It didn't fail, but it didn't allow me to write to that uart. No errors were generated but nothing.

So my question is what pins are board.TX and board.RX on the Metro ESP32-S2??

jfabernathy
 
Posts: 45
Joined: Thu Dec 17, 2020 10:58 pm

Re: Debug UART port on Metor ESP32-S2 board

by tannewt on Tue Jan 12, 2021 12:40 pm

RX is 5 and TX is 6. All of the pin definitions are here: https://github.com/adafruit/circuitpyth ... 2s2/pins.c

tannewt
 
Posts: 2034
Joined: Thu Oct 06, 2016 8:48 pm

Re: Debug UART port on Metor ESP32-S2 board

by jfabernathy on Tue Jan 12, 2021 1:25 pm

tannewt wrote:RX is 5 and TX is 6. All of the pin definitions are here: https://github.com/adafruit/circuitpyth ... 2s2/pins.c

This worked great. I now have a solution.

jfabernathy
 
Posts: 45
Joined: Thu Dec 17, 2020 10:58 pm

Please be positive and constructive with your questions and comments.