Using ESP32-C3 QT Py with Zephyr RTOS?

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tamberg
 
Posts: 31
Joined: Wed May 07, 2014 1:09 pm

Using ESP32-C3 QT Py with Zephyr RTOS?

Post by tamberg »

Hi,

I'm trying to get the Adafruit QT Py ESP32-C3 WiFi Dev Board [0] to work with Zephyr RTOS.

The ESP32-C3 Dev Module seems to be supported [1].

However the hello world [2] does not seem to work.

Compiling and flashing seems to work, but there's no serial output.

UART Pins seem to be the same on the QT Py, according to pinout [3].

Is there any other substantial difference between the QT Py and Dev Module?

[0] https://www.adafruit.com/product/5405
[1] https://docs.zephyrproject.org/latest/b ... index.html
[2] https://github.com/zephyrproject-rtos/z ... src/main.c
[3] https://learn.adafruit.com/assets/109663
Last edited by tamberg on Fri May 27, 2022 9:26 am, edited 6 times in total.

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tamberg
 
Posts: 31
Joined: Wed May 07, 2014 1:09 pm

Re: How does ESP32-C3 QT Py differ from Dev Module?

Post by tamberg »

Here's the boot log

Code: Select all

 $ west espressif monitor                             
Serial port /dev/cu.usbmodem14201
Connecting...
Detecting chip type... ESP32-C3
/Users/tamberg/Documents/Zephyr/zephyrproject/zephyr/../modules/hal/espressif/tools/idf_monitor.py:553: DeprecationWarning: distutils Version classes are deprecated. Use packaging.version instead.
  if StrictVersion(serial.VERSION) < StrictVersion('3.3.0'):
--- idf_monitor on /dev/cu.usbmodem14201 115200 ---
--- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
ESP-ROM:esp32c3-api1-20210207
Build:Feb  7 2021
rst:0x15 (USB_UART_CHIP_RESET),boot:0xf (SPI_FAST_FLASH_BOOT)
Saved PC:0x4004c62e
SPIWP:0xee
mode:DIO, clock div:2
load:0x3fcd6100,len:0x187c
load:0x403ce000,len:0x8bc
load:0x403d0000,len:0x2b88
SHA-256 comparison failed:
Calculated: c4be69e6a7ac07ecc9e707fe373b06cb277bd0273eff07a21fc421e14d21b4b3
Expected: 0a150bf58a9ca5e043b2495baad4119be81c5de6fe99e9d9caa393a77e7ec9b8
Attempting to boot anyway...
entry 0x403ce000
I (43) boot: ESP-IDF release/v4.3-176-g5a334d558 2nd stage bootloader
I (43) boot: compile time 13:50:06
I (43) boot: chip revision: 3
I (46) boot.esp32c3: SPI Speed      : 40MHz
I (51) boot.esp32c3: SPI Mode       : DIO
I (56) boot.esp32c3: SPI Flash Size : 4MB
I (61) boot: Enabling RNG early entropy source...
I (66) boot: Partition Table:
I (70) boot: ## Label            Usage          Type ST Offset   Length
I (77) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (84) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (92) boot:  2 factory          factory app      00 00 00010000 00100000
I (99) boot: End of partition table
I (103) boot_comm: chip revision: 3, min. application chip revision: 0
I (111) esp_image: segment 0: paddr=00010020 vaddr=00000020 size=0001ch (    28) 
I (119) esp_image: segment 1: paddr=00010044 vaddr=3fc849f0 size=00094h (   148) load
I (127) esp_image: segment 2: paddr=000100e0 vaddr=3fc84a84 size=00200h (   512) load
I (136) esp_image: segment 3: paddr=000102e8 vaddr=40380000 size=03648h ( 13896) load
I (148) esp_image: segment 4: paddr=00013938 vaddr=00000000 size=0c700h ( 50944) 
I (163) esp_image: segment 5: paddr=00020040 vaddr=3c000040 size=00668h (  1640) map
I (164) esp_image: segment 6: paddr=000206b0 vaddr=00000000 size=0f968h ( 63848) 
I (183) esp_image: segment 7: paddr=00030020 vaddr=42010020 size=03bbch ( 15292) map
I (187) boot: Loaded app from partition at offset 0x10000
I (188) boot: Disabling RNG early entropy source...

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