Use of second core on RP2040?

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SeattleDavid
 
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Use of second core on RP2040?

Post by SeattleDavid »

From what I read, there is no ability to utilize the second core on the RP2040 (Pico). My understanding is that this is because CircuitPython is side-stepping concurrency issues.

Am I correct?

And is there discussion or are there plans to eventually allow a second core to be utilized?

It seems that supporting a second core could be done in a useful way while sidestepping concurrency by requiring the two cores to be loosely coupled…allocate specific IO pins to one core or the other, allocate a block of memory unique to each core, and allow the cores to communicate only through a message pipe/queue. There might be some restrictions.

This would allow the UI to run in one core without having to be very polite about cooperative multitasking. It would allow timing critical stuff to run on its own core, independent of piggy stuff on the other core. It would in some ways be like a “Super PIO” that could do complex but isolated things independently.

As a learning tool, the ability to utilize two cores (even if very independent) has value since multi-cores is increasingly the norm anymore.

Any revelations, corrections, or insights to offer about this?

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danhalbert
 
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Re: Use of second core on RP2040?

Post by danhalbert »

This is discussed in https://github.com/adafruit/circuitpython/issues/4106. We are also thinking about how to use the coprocessor interface developed for the ULP on Espressif: https://github.com/adafruit/circuitpython/pull/7359. That is an independent program running on a second processor, with shared memory slots.

Yes, figuring out pin contention and the like is a problem to be solved.

Adding general multiprocessor support could really use an underlying RTOS. There is none on the current RP2040 port.

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SeattleDavid
 
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Re: Use of second core on RP2040?

Post by SeattleDavid »

OK, so "Not today" but possibly sometime in the future.

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SeattleDavid
 
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Re: Use of second core on RP2040?

Post by SeattleDavid »

A suggestion:

Just treat the second core as if it was a second Pico chip that is literally wired on top of the first chip. Two processors, operating completely independently of each other. The user can self-manage which pins to use. That would be a good start.

Now, add into the mix an inter-processor message queue so that messages can be passed between them.

Wouldn't this be simple to implement, simple to understand, and meet about 98% of the needs of people?

It seems like it would sidestep almost all of the concurrency complexities. (Perhaps I am missing something.)

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